Write buffer design for cache-coherent shared-memory multiprocessors

We evaluate the performance impact of two diier-ent write{buuer conngurations (one word per buuer entry and one block per buuer entry) and two diierent write{policies (write{through and write{back), when using the partial block invalidation coherence mechanism 3] in a shared{memory multiprocessor. Using an execution{driven simulator, we nd that the one word per entry buuer connguration with a write{back policy is preferred for small write{buuer sizes when both buuers have an equal number of data words, and when they have equal hardware cost. Furthermore, when partial block invalidation is supported, we nd that a write{through policy is preferred over a write{ back policy due to its simpler cache hit detection mechanism , its elimination of write{back transactions, and its competitive performance when the write{buuer is relatively large.